 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Standard ICs Segment-type LCD driver BU9729K The BU9729K is a driver for segmented liquid crystal displays, which enables connection with a microcomputer through a serial interface. 4-bit common output and an internal power supply circuit for LCD drive make it possible to configure a low-cost display system. *Applications car audio equipment, telephones Movie projectors, *Features (8-bit length). 1) Serial interface 2) Display RAM: 72bits, internal (up to 72 segments can be displayed). 3) Internal power supply circuit for liquid crystal drive. 4) Display duty: 1 / 4. 5) Low-voltage and low-current operation supported. *Block diagram VLCD VC LCD Driver Bias Circuit VDD VSS SEG1 SD SCK C/D CS Serial Interface Address Counter Display Data RAM (DD RAM) LCD Segment Driver 18bits SEG18 SEG2 Command / Data Register LCD Common Driver 4bits COM1 COM2 COM3 COM4 Command Decoder Timing Generator Common Counter OSC1 OSC2 1 Standard ICs BU9729K *Pin assignments SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 17 16 SEG2 15 24 SEG11 25 23 22 21 20 19 18 SEG12 26 SEG1 SEG13 27 14 COM4 SEG14 28 13 COM3 SEG15 29 12 COM2 SEG16 30 11 COM1 SEG17 31 10 C/D SEG18 32 1 2 3 4 5 6 7 8 9 CS OSC1 OSC2 VLCD VDD VC SCK VSS Fig.1 2 SD Standard ICs BU9729K *Pin descriptions Pin name OSC1 OSC2 VSS VC VLCD VDD SCK Pin No. 1 2 3 4 5 6 7 -- I I/O I O -- -- Function These are the I / O pins for the internal oscillator. Resistance should be connected between the pins when the internal clock is operating. When an external clock is operating, input should be done from OSC1, and OSC2 should be left open. This is the VSS pin. This is the power supply pin for LCD drive. The condition VLCD This is the VDD pin. This is the shift lock input pin for serial data. The contents of the SD pin are read one bit at a time at the rising edge of this pin. This is the serial data input pin. SD 8 I Display data and commands are input here. When this is "0", display data is not displayed, and when "1", the data is displayed. This is the chip select signal input pin. CS 9 I When this is LOW, SD input can be received. The SCK counter is incremented at the timing at which CS goes from HIGH to LOW. This is the signal input which recognizes whether the SD input consists of commands or display data. C/D 10 I When the SCK of the eighth clock rises, this pin judges the input to be display data if the level is LOW, and a command if the level is HIGH. COM1 ~ COM4 SEG1 ~ SEG18 15 ~ 32 O These are the segment output pins for LCD drive. They are connected to the segments of the LCD panel. 11 ~ 14 O These are the common output pins for LCD drive. They are connected to the commons of the LCD panel. VC VSS must be satisfied. *Absolute maximum ratings (Ta = 25C, VSS = 0V) Parameter Power supply voltage 1 Power supply voltage 2 Power dissipation Operating temperature Storage temperature Input voltage Output voltage Symbol VDD VLCD Pd Topr Limits - 0.3 ~ + 7.0 - 0.3 ~ + 7.01 4002 - 20 ~ + 75 - 55 ~ + 125 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 Unit V V mW C C V V Tstg VIN VOUT 1 The condition VLCD VC VSS must be satisfied. 2 Reduced by - 4.0mW for each increase in Ta of 1C over 25C. 3 Standard ICs BU9729K *Recommended operating conditions (Ta = 25C, VSS = 0V) Parameter Power supply voltage 1 Power supply voltage 2 Oscillation frequency Symbol VDD VLCD fOSC Min. 2.5 2.5 -- Typ. -- -- 36 Max. 5.5 5.5 -- Unit V V kHz Conditions -- The condition VLCD Rf = 470k VC VSS must be satisfied. *Electrical characteristics otherwise noted, VDD = 2.5V to 5.5V, VSS = 0V, Ta = 25C) DC characteristics (unless Parameter Input high level voltage Symbol VIH1 Min. Typ. -- Max. VDD 0.2 x VDD RON IIL2 IIH CI -- -- -2 -- -- Current consumption IDD -- -- -- -- -- -- 5 0.05 8 40 100 30 2 -- -- 1 25 80 250 Unit V Conditions -- Applicable pin OSC1, SD, SCK, C / D, CS 0.8 x VDD Input low level voltage LCD driver on-resistance1 Input high level current 2 Input low level current Input capacitance VIL1 0 -- V k A A pF A A A A -- VON = 0.1V VIN = 0 VIN = VDD -- While quiescent2 When "ALL OFF" is displayed For display operations3 For access operations4 VDD -- SEG1 ~ 32, COM1 ~ 4 OSC1, SD, SCK, C / D, CS OSC1, SD, SCK, C / D ,CS SD,SCK, C / D, CS 1 The internal power supply impedance is not included in the LCD driver on-resistance. 2 All input is fixed at either VDD or VSS. 3 Except for Rf = 470k and OSC1, all input is fixed at VDD or VSS. 4 Rf = 470k, fSCK = 200kHz. AC characteristics (unless otherwise noted, VDD = 2.5V to 5.5V, VSS = 0V, Ta = 25C) Parameter SCK rise time SCK fall time SCK cycle time Command wait time SCK pulse width HIGH SCK pulse width LOW Data setup time Data hold time CS pulse width HIGH CS pulse width LOW CS setup time CS hold time C / D setup time C / D hold time C / D-CS time5 C / D-SCK time5 Symbol tTLH tTHL tCYC tWAIT tWH1 tWL1 tSU1 tH1 tWH2 tWL2 tSU2 tH2 tSU3 tH3 tCCH tSCH Min. -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 100 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions -- -- -- -- -- -- -- -- -- -- -- -- -- 800 800 300 300 100 100 300 6400 100 100 100 100 100 100 8th rise of SCK used as reference CS rise used as reference 8th fall of SCK used as reference 5 Should satisfy either one of these conditions. 4 Standard ICs BU9729K *Input / output circuits Pin name SD SCK C/D CS I/O I Equivalent circuit Pin name SEG1 ~ SEG18 VDD COM1 ~ COM4 GND I/O O VLCD Equivalent circuit IN OUT VLCD GND OSC1 OSC2 I O VDD OSC1 OSC2 GND 5 Standard ICs BU9729K *Timing charts tWL2 tWH2 CS tSU2 tCYC tWH1 SCK tWL1 tSU1 SD tSCH tCCH tSU3 tH3 tTLH1 tH1 tTHL tH2 C/D Fig. 2 Interface timing tCYC tWA / T SCK SD D7 D6 D0 D7 Fig. 3 Command cycle format *Datadata is transmitted using four-line clock synchronous transmission. Serial data with a length of eight bits is Serial input synchronized to SCK. If C / D is HIGH at the rise of the 8 x nth clock of SCK, the serial data is recognized as a command, and if C / D is LOW, the serial data is recognized as display data. Serial data is input sequentially, starting from the MSB. 6 Standard ICs BU9729K *Detailed explanation of commands at the 8 x nth clock of SCK) are available for the BU9729K. The following commands (C / D is HIGH (1) Address Set MSB LSB 0 0 0 A A A A A Address data displayed in binary format as AAAAA is set for the address counter. The address is incremented by two each time input of the display data (8 bits of data) is completed. (2) Display On MSB LSB 0 0 1 : Don't Care All displays light, regardless of the contents of the display data RAM (DDRAM). At this point, the contents of the DDRAM do not change. (3) Display Off MSB LSB 0 1 0 : Don't Care All displays go out, regardless of the contents of the DDRAM. At this point, the contents of the DDRAM do not change. (4) Display Start MSB LSB 0 1 1 : Don't Care The display begins, in accordance with the contents of the DDRAM. (5) Display Data RAM (DDRAM) Write MSB LSB 1 0 0 D D D D : Don't Care The binary 4-bit data DDDD is written to the DDRAM. The address is that specified by the Address Set command. After this command is executed, the address is automatically incremented by + 1. 7 Standard ICs (6) Reset MSB LSB BU9729K 1 1 0 : Don't Care This command should be executed after the power supply has been turned on and before any other command is executed. This command causes the BU9729K to initialize the following: Display Off Address Counter Reset *Description of functions (1) Register The BU9729K has an 8-bit command / data register. Serial data is read in 8-clock units of SCK. If the data read into the register is displayed data (C / D is LOW at the eighth clock of SCK), it is written to the DDRAM. If it is command data (C / D is HIGH at the eighth clock of SCK), it is output to the command decoder to control the BU9729K. (2) Address counter The address counter indicates DDRAM addresses. When the Address Set command is written to a command or data register, the address data is sent automatically to the address counter. After data has been written to the DDRAM, the address counter increments automatically by either + 1 or + 2. The amount by which the counter increments is determined automatically, based on the following status. DDRAM 8-bit writing (C / D is LOW at the eighth clock of SCK) + 2 DDRAM 4-bit writing (C / D is HIGH at the eighth clock of SCK) + 1 When the address counter has counted to the address 11H, it becomes 00H the next time it is incremented. (3) Display data RAM (DDRAM) The display data RAM (DDRAM) is used to store display data. It has a capacity of 18 addresses x 4 bits. The relationship between the DDRAM and the display position is shown below. DD RAM address 00 01 02 03 04 05 06 07 ********* 0F 10 11 0 COM1 1 COM2 2 COM3 3 COM4 8 Standard ICs BU9729K DDRAM addresses set for the address counter are in hexadecimal format, and are displayed as shown below. MSB LSB AC4 AC3 AC2 AC1 AC0 (Example) When the DDRAM address is "11" (display position: SEG18) MSB LSB 1 0 0 0 1 1 1 Display data input to the command / data register (C / D = LOW) is divided into the first four bits and the last four bits, with the specified DDRAM address being written to the first four, and the specified address + 1 being written to the last four. The four bits of display data are written sequentially to the bits of the DDRAM, starting from the MSB on both sides. MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Specified address (bit3 bit0) (bit3 Specified address + 1 bit0) When a DDRAM Write command is input (C / D = HIGH), the four bits of display data in the DDRAM Write command are written to the specified DDRAM address. The four bits are written sequentially, starting from the MSB, to the bits of the DDRAM, starting with the MSB of the DDRAM. MSB LSB 1 0 0 D3 D2 D1 D0 DDRAM Write command (bit3 Display data bit0) (4) Timing generator Connecting Rf between OSC1 and OSC2 causes oscillation of the internal oscillator circuit and generates a display timing signal. Operation can also be initiated by inputting an external clock. OSC1 Rf OSC2 (Rf can be used to change the oscillation frequency.) OSC2 OPEN OSC1 EXIT CLOCK INPUT Fig. 4 Rf oscillator circuit Fig. 5 External clock input 9 Standard ICs BU9729K (5) LCD driver power supply The LCD driver power supply is generated by the BU9729K. V1 = 2 * VC / 3, V2 = VC / 3 is generated internally. VDD VLCD VC VSS Fig. 6 Example of power supply connection (6) LCD drive circuit The LCD drive circuit is configured of 4 common drivers and 18 segment drivers. When oscillation begins, any effective common output automatically outputs a selective waveform, while the others output non-selective waveforms. Segment output automatically outputs drive waveforms, based on the display data and common counter. The common and segment output waveforms are shown in the following examples. 10 Standard ICs BU9729K *LCD drive waveforms Frame interval VC V1 COM1 V2 VSS VC V1 COM2 V2 VSS VC V1 COM3 V2 VSS VC V1 COM4 V2 VSS VC V1 V2 VSS VC V1 V2 VSS VC SEG1 SEG18 ~ V2 VSS VC V1 V2 VSS VC V1 V2 VSS 1 1 1 1 (All SEGn corresponding from COM1 to COM4 are displayed.) 0 1 0 1 (Only SEGn corresponding to COM2 and COM4 are displayed.) V1 0 1 0 0 (Only SEGn corresponding to COM2 are displayed.) 1 0 0 0 (Only SEGn corresponding to COM1 are displayed.) COM1 COM2 COM3 COM4 0 0 0 0 (No SEGn corresponding from COM1 to COM4 are displayed.) Fig. 7 11 Standard ICs VDD has to satisfy the following conditions. Instruction receipt possible VDD 2.5V tWAIT < 1ms VDD < 0.3V 0 < tON < 10ms BU9729K *External dimensions (Units: mm) 9.0 0.3 7.0 0.2 24 9.0 0.3 7.0 0.2 25 32 1 1.45 0.1 0.05 8 17 16 9 0.4 0.15 0.1 0.15 0.8 0.4 0.1 QFP32 12 |
Price & Availability of BU9729K
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |